1. Field of the Invention
The present invention relates to an ion implantation apparatus which implants ions into substrates such as silicon wafers, and in particular to an ion implantation apparatus and ion implantation method which combine prevention of wafer droppage in replacement operations and inhibition of pin mark occurrence.
Priority is claimed on Japanese Patent Application No. 2008-173621, filed Jul. 2, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
From the standpoint of fabrication of semiconductor devices which have high speed and low power consumption, SOI (Silicon on Insulator) substrates are the focus of attention. SOI substrates have embedded oxide film with excellent insulation properties, and a thin silicon layer (SOI layer) which covers this. In SOI substrates, this silicon layer is used as the active layer, thereby enabling achievement of semiconductor devices with higher integration, lower power consumption, higher speed, high reliability, and so on.
This type of SOI substrate is manufactured by the bonding method that bonds together two wafers with interposition of oxide film, and SIMOX (Separation by Implanted Oxygen) method, or the like (e.g., see the Specification of U.S. Pat. No. 5,930,643). With the SIMOX method, an ion implantation apparatus is used, and oxygen ions are implanted into silicon wafers in a heating environment on the order of 400-600° C., after which an oxide film is formed within the silicon wafer by higher heating (annealing) to manufacture the SIMOX wafer (SOI substrate). As an ion implantation apparatus which uses the SIMOX method, there is, for example, the one disclosed in Japanese Unexamined Patent Application, First Publication No. 2003-45371.
The ion implantation apparatus recorded in Japanese Unexamined Patent Application, First Publication No. 2003-45371 has a wheel-type substrate support member, substrate holders which are provided with interposition of a hub and arms of the substrate support member, and a beam liner which generates an ion beam. The wafer is held by the substrate holder on a wafer conveyor which is an accessory to the ion implantation apparatus, and is scanned with an ion beam by the rotation of the substrate support member and the oscillation of the hub. After the treatment surface of the wafer has been implanted with ions by irradiation with an ion beam, the wafer is carried to the conveyor by the rotation of the substrate support member, and is discharged.
In the Specification of U.S. Pat. No. 6,794,662, a configuration is proposed wherein the substrate holder of ion implantation apparatus adopts a pin structure which holds the wafer with multiple substrate holding pins; holding is accomplished by having the multiple substrate holding pins contact the circumferential edge of the wafer. In an ion implantation apparatus provided with this structure, the wafer holding mechanism in the substrate holder can be simplified, the contact area of the wafer and the substrate holder can be reduced, and damage to the wafer due to rubbing during holding of the wafer can be inhibited.
Moreover, the substrate holding pins of the Specification of U.S. Pat. No. 6,794,662 are formed with thermohardening resin. In the case where the substrate holding pins are formed with metal material, metal sputtering occurs due to irradiation of the substrate holding pins with an ion beam, risking contamination of the wafer. However, when the substrate holding pins are formed with resin material, there is no risk of such contamination, and satisfactory ion implantation is possible.
As the most important specification of SOI substrates, there is the layer thickness of the SOI layer, which is separated from the bulk of the silicon wafer by the oxide film. As the layer thickness of the SOI layer has major effects on the conditions of the device fabrication process using an SOI substrate and on device properties, it is not only required that layer thickness be as designed, but also that the SOI substrate be of uniform thickness so that disparities in the layer thickness of the SOI layer within the wafer are non-existent to the extent possible.
With the ion implantation apparatus of the Specification of U.S. Pat. No. 6,794,662, a structure is adopted wherein a recess or taper is provided on the side face of the substrate holding pins, the wafer is engaged, and holding of the wafer is stably conducted. However, in the case of such the structure, a portion of the substrate holding pin protrudes over (planarly overlaps) the treatment surface of the wafer, with the result that the substrate holding pin blocks the ion beam with this protruding portion. When this occurs, ion implantation of the portions that are shaded by the substrate holding pins is obstructed, giving rise to sites of ion implantation deficiency called “pin marks”. When this occurs, layer thickness disparities arise in the SOI layer that is formed, with the result that usable wafer surface area is reduced.
In order to prevent pin mark occurrence, it is conceivable to reduce the portion of the substrate holding pin that protrudes over the wafer. However, in the case where the portion of the pin protruding over the wafer is small, the holding of the wafer is unstable. In addition, ion implantation treatment is conducted in a heated environment, and the environmental temperature during this time is a temperature that is equal to or greater than the glass transition temperature of ordinary thermohardening resin, with the result that substrate holding pins of resin material tend to soften, and holding tends to loosen. In this case, there is a risk that the following type of problem may occur.
As wafer conveyance is easy, wafers are often moved/conveyed in a state where their planar direction is horizontal. In contrast, in an ordinary ion implantation apparatus, in order to prevent the wafer from undergoing warpage or deformation due to its own weight in a high temperature environment, the wafer is raised upright from its horizontal state, and ion implantation is conducted. Consequently, in an ion implantation apparatus, it is frequently the case that an untreated wafer is horizontally loaded, after which operations are conducted whereby the wafer is turned, and raised upright. In the case where such turning operations are conducted, the wafer tends to fall off when holding by the substrate holding pins loosens.
With respect to such turning operations, when cooling is conducted, for example, until 250° C. or less, and replacement operations are conducted, the resin that was softened at high temperature is cooled, and its flexural strength is restored, enabling prevention of wafer droppage. However, in this case, time is required for cooling, and reheating is required for the ion implantation treatment that is to subsequently follow, resulting in reduced productivity.
The present invention was made in light of such circumstances, and its object is to offer an ion implantation apparatus and ion implantation method which make it possible to combine prevention of wafer droppage in replacement operations and inhibition of pin mark occurrence at the periphery of the holding pins.